1. Technical Field of the Invention
This invention relates generally to circuits for generating voltage rails, and more specifically to an improved charge pump for generating voltage rails.
2. Background Art
FIG. 1 illustrates a charge pump circuit 10 which is known in analog and power semiconductor design. The charge pump is built around a flying capacitor CF, four controllable switches S1 to S4, and capacitor CP. The capacitor CP can be referred to as a storage or bypass capacitor. A first switch SA and a third switch SC are coupled to a first terminal of the flying capacitor, and a second switch SB and a fourth switch SD are coupled to a second terminal of the flying capacitor. The first and second switches are operated together by a first phase control signal PHI1, and the third and fourth switches are operated together by a second phase control signal PHI2. The phase control signals are typically operated as binary clock signals 180° out of phase, and can be a clock signal and an inverted version of that clock signal with the addition of some dead time at each transition, when no switch is on. The dead time is important, to ensure that SB and SD do not produce a short between 50P and GND, and to ensure that SA and SC do not produce a short between VDD and 50P.
The first switch un/couples the first terminal of the flying capacitor from/to the VDD voltage reference supply. The fourth switch un/couples the second terminal of the flying capacitor from/to the ground (GND) voltage reference supply. The second switch un/couples the second terminal of the flying capacitor from/to an output terminal 50P at which the charge pump generates VDD/2. And the third switch un/couples the first terminal from/to the output terminal. The storage capacitor CP is coupled between the output terminal and the ground voltage reference supply in order to store the charge packets delivered by CF and to smooth the voltage at 50P.
FIGS. 2 and 3 show the two charge pump states (during assertion of PHI1, and assertion of PHI2, respectively) of the charge pump of FIG. 1. During PHI1, the flying capacitor is effectively coupled between VDD and the output node. During PHI2, the flying capacitor is effectively coupled between the output node and GND.
FIG. 4 illustrates a voltage rail generation circuit 20 according to the prior art. In addition to the voltage reference inputs VDD and GND, the voltage rail generation circuit uses three of the FIG. 1 charge pumps CP50, CP75, and CP25 to generate three intermediate voltage rails: VDD*0.50 at terminal 50P, VDD*0.75 at terminal 75P, and VDD*0.25 at terminal 25P, respectively. The primary charge pump CP50 is coupled to VDD and GND, and generates an output voltage equal to (VDD+GND)/2. The second charge pump CP75 is coupled to VDD and CP50, and generates an output voltage equal to (VDD+CP50)/2. The third charge pump CP25 is coupled to CP50 and GND, and generates an output voltage equal to (CP50+GND)/2.
Unfortunately, each of the charge pumps requires its own, dedicated flying capacitor (CF50, CF75, and CF25) and its own storage capacitor (C50P, C75P, and C25P). What is needed is an improved voltage rail generation circuit which does not require a dedicated flying capacitor for every voltage rail generated, while still maintaining the high efficiencies that charge pumps can obtain. It is desirable to minimize the flying capacitors, because they tend to have tighter ESR requirements than the storage capacitors and when integrated into an integrated circuit each flying capacitor requires two added pins which increases the cost of the integrated circuit.